High energy sub-atomic particles occasionally hit integrated circuit (IC) devices and cause interference. When an energetic particle hits an IC chip it may ionize an atom within the circuitry and thereby cause a single event effect to occur. There are several types of single event effects that can occur. The more severe effects include single event burnout and single event latchup. A less severe type of single event effect is a single event upset (SEU).
An SEU is a change of state or a transient pulse through an IC device caused by an ionizing particle. An SEU will manifest itself either by flipping the state of a sequential logic component (such as a memory or a flip-flop), commonly referred to as a “bit flip,” or by introducing a transient pulse through a circuit that temporarily alters the values passing through combinational logic.
An SEU typically does not permanently affect the device and the device will continue to operate normally after the SEU occurs, although data may be corrupted. SEU and other single event effects are very common in outer space beyond the protection of the Earth's atmosphere against cosmic radiation. Therefore, IC devices used in outer space must be specially designed to limit this problem. On Earth, most energetic particles that could cause SEU are blocked by the atmosphere. However, energetic neutrons often make it through to the ground.
The neutron flux in New York City is approximately 14-20 neutrons per hour per square centimeter. However, at higher altitudes, the flux increases. For example, in Denver, Colo., the neutron flux is about 7 or 8 times higher than in New York City. Similarly, the flux is high on a commercial or military airplane flight. SEU has traditionally been much more prevalent in memory devices, particularly within SRAM. However, as device geometries shrink and clock speeds increase, SEU is becoming more prevalent in logic circuits. The SEU error rate in logic circuits is beginning to approach the rate found in memory devices of similar geometries.
It is possible to test an IC device for SEU. This usually involves applying a high energy particle beam at the device and counting the number of SEU's observed. One conventional method of doing this is by operating the device in normal mode and analyzing portions of the device at a time by counting errors in multiple signal lines at once. Another conventional method utilizes scan chains to test for SEU in sequential logic by leaving the sequential logic to be tested unclocked (i.e., in a static state) while applying the particle beam and then re-applying the clock in order to scan out the data within the scan chain and count the errors.
This type of SEU testing can be expensive and time consuming. Accordingly, there is a need to be able to efficiently test the susceptibility of a circuit to SEU errors. Likewise, there is a need by which to inject faults such as those introduced by Single Event Transient (SET) into a circuit so as to then test the susceptibility of the circuit to the faults and SEUs.